MIMO-OFDM for 100G+/LANE Chip-to-Chip connection: SerDes, Highspeed I/O
Published:
Introduction of the MIMO-OFDM based highspeed IO
With the ongoing increase in demand for higher System-on-Chip (SoC) I/O speeds, the significance of data rates for chip-to-chip (C2C) and chip-to-module (C2M) communication is becoming more crucial than ever. The adoption of PMA4 has become prevalent in SerDes design, and even the consideration of PAM8 modulation is on the horizon. However, while the relatively simple architecture of NRZ, PAM4, and PAM8 offers advantages, these modulation formats also suffer from suboptimal spectrum efficiency. This challenge is particularly pronounced when limitations in PCB or substrate RF bandwidth act as bottlenecks for achieving desired data throughput performance.